1. Field of the Invention
The present invention relates to a filter device capable of generating a filtered output signal free from overshoot and undershoot possibly occurring in an output of a low pass digital filter used for digital image signal processing and the like.
2. Description of the Related Art
Conventionally, there is known a lowpass filter device (for passing low frequency components therethrough) for filtering out high frequency components of a video signal, for example, in digital image signal processing.
FIG. 2 is a schematic diagram of a conventional filter device for use in the digital image signal processing.
This filter device comprises a low pass FIR (Finite Impulse Response) digital filter 10 having a filter length corresponding to, for example, five stages, and a limiter circuit 20 for limiting a maximum value and a minimum value of an output of the digital filter 10.
The FIR digital filter 10 comprises a shift register composed of flip-flops (hereinafter referred to as the “FF”) 11-0 to 11-4 chained together and having five stages for shifting an n-bit digital input signal Y[n−1:0] at the respective stages; five multiplier circuits 12-0 to 12-4 for multiplying internal latch data w0[n−1:0] to w4[n−1:0] latched by the FF 11-0 to 11-4 at the respective stages by predetermined filter coefficients A(0) to A(4), respectively; and adder circuits 13-1 to 13-4 chained together and having four stages for summing output signals from the respective multiplier circuits 12-0-12-4 to supply a filtered signal Limit_in[n−1:0].
The filter coefficient A(M) (where M=0, 1, 2, 3, 4) determines the frequency characteristics of the digital filter 10, and is calculated by the following Equation (1):A(M)=(ωp*T/π)*S((n−L)*ωp*T),  (1)where ωp*T=2π*(Fp/Fs),                S(x)=sin(x)/X,        ωp: Passband Edge Angular Frequency;        Fp: Passband Edge Frequency;        Fs: Sampling Frequency; and        L: Group Delay.        
The limiter circuit 20 is a circuit for limiting a maximum and a minimum of the output signal Limit_in[n−1:0] from the digital filter 10 based on a fixed maximum value Max[n−1:0] and a fixed minimum value Min[n−1:0] to supply a signal Limit_out[n−1:0]. In regard to the fixed maximum value Max[n−1:0] and the fixed minimum value Min[n−1:0], for example, in a composite signal, a separate Y (luminance) signal, and a sync-on green signal, the minimum value Min[n−1:0] is often set to −40 IRE which is an “L” level of a horizontal synchronization signal and is referred to as a sync tip level. The maximum value Max[n−1:0] is often set to 100 IRE or higher which is specified by CCIR 601 industrial standard of video. Here, IRE (Institute of Radio Engineers) is a unit representing a relative ratio of a video signal. A video signal portion is defined a range from 0 IRE to 100 IRE.
The filter device of FIG. 2 operates in the following manner.
On receiving a digital input signal Y[n−1:0] as a video signal, FF 11-0 to 11-4 latch and shift the input signal Y[n−1:0] at the respective stages. Internal latch data w0[n−1:0] to w4[n−1:0] supplied from the FF 11-0 to 11-4 at the respective stages are multiplied by filter coefficients A(0) to A(4), respectively, by the respective multiplier circuits 12-0 to 12-4. The results of the multiplications are summed by the adder circuits 13-1 to 13-4, and an output signal Limit_in[n−1:0] from which high frequency components have been removed is supplied from the adder circuit 13-4 at the last stage.
When a maximum value of the output signal Limit_in[n−1:0] is larger than a predefined value or when a minimum value of the output signal Limit_in[n−1:0] is smaller than a predefined value, subsequent circuits will be adversely affected, so that the maximum and minimum values of the output signal Limit_in[n−1:0] are limited by the limiter circuit 20 within a fixed maximum value Max[n−1,0] and a fixed minimum value Min[n−1:0]. Generally, since the fixed maximum value Max[n−1,0] is set larger than the maximum value of the output signal Limit_in[n−1:0], and the fixed minimum value Min[n−1:0] is set smaller than the minimum value of the output signal Limit_in[n−1:0], the output value Limit_in[n−1:0] passes through the limiter circuit 20 as it is, and is supplied as the signal Limit_out[n−1:0].
In the filter device of FIG. 2, the filter length of the filter 10 should be as long as possible, and ideally infinite. However, when the filter 10 is mounted, for example, in a semiconductor integrated circuit, the filter length must be limited due to physical limitations. Equation (1) for calculating the filter coefficients A(M) (M=0, 1, 2, 3, or 4) includes a SIN function, so that the filter coefficient A(M) can be a negative value. The filter 10 which has a short limited filter length and can generate a negative filter coefficient A(M) will cause an increase in the weight of the filter coefficient A(M). This results in, when the waveform of the input signal Y[n−1:0] abruptly rises or falls down from a temporally constant level, overshoot and undershoot occurring in the output signal Limit_out[n−1:0] (=Limit_in[n−1:0]) of the limiter circuit 20.
FIGS. 3 to 5 are diagrams illustrating the cause of the overshoot and undershoot generated in the filter device of FIG. 2, where FIG. 3 is a waveform chart showing the relationship between the output signals of the respective multiplier circuits 12-0 to 12-4 in FIG. 2 and the output signal Limit_out[n−1:0] (=Limit_in[n−1:0]) of the filter 10 when the input signal Y[n−1:0] changes from zero to N (in arbitrary units); FIG. 4 is a waveform chart showing the relationship between the internal latch data w0[n−1:0] to w4[n−1:0] and the output signal Limit_out[n−1:0] (=Limit_in[n−1:0]) of the filter 10; and FIG. 5 is a waveform chart showing the input signal Y[n−1:01] (broken-line curve) and the output signal Limit_out[n−1:0] (=Limit_in[n−1:0]) (solid-line curve) in FIG. 2.
A transfer function H(z) of the filter device in FIG. 2 is expressed by, for example, the following Equation (2):
                              H          ⁡                      (            z            )                          =                                            -              0.0928                        *                          Z              ⁡                              (                                  -                  2                                )                                              +                      0.302            *                          Z              ⁡                              (                                  -                  1                                )                                              +                      0.58            *                          Z              ⁡                              (                0                )                                              +                      0.302            *                          Z              ⁡                              (                                  +                  1                                )                                              +                                    (                              -                0.092                            )                        *                                          Z                ⁡                                  (                                      +                    2                                    )                                            .                                                          (        2        )            
In time units T0 to T2 in FIGS. 3 and 4, the input signal Y[n−1:0] has a value of “0” and the output signal Limit_in[n−1:0] of the filter 10 also has a value of “0.” In time unit T3, the input signal Y[n−1:0] changes to N. In the time unit T4, the output of the multiplier circuit 12-0 has a value of “−0.019*N.” Since the values of the input signals w1[n−1:0] to w4[n−1:0] of the remaining multiplier circuits 12-1 to 12-4 are “0,” and the value of the output is “0.” Consequently, the output signal Limit_in[n−1:0] has a value of “−0.019*N” which is less than “0” and passes through the limiter circuit 20 as it is, causing undershoot 22 to occur as shown in FIG. 5. The filter coefficients A(M) are calculated such that they are summed up to be one, so that when only the input signal w4[n−1:0] of the multiplier circuit 12-4 has a value of “0” in time unit T7, the output signal Limit_in[n−1:0] of the filter 10 has a value of “N*1.092” which is larger than N and passes through the limiter circuit 20 as it is, causing overshoot 21 to occur as shown in FIG. 5.
As shown in FIG. 4, the value of the overshoot 21 is larger than the internal latch data w0[n−1:0] to w4[n−1:0], while the value of the undershoot 22 is smaller than the internal latch data w0[n−1:0] to w4[n−1:0]. The same applies when the input signal Y[n−1:0] changes from N to zero.
In a composite signal which is a video signal, the excessive overshoot 21 and undershoot 22 cause a receiver to falsely detect vertical and horizontal synchronization signals, resulting in instable images. Also, a luminance component can be mixed into a color component, giving rise to degraded image quality. In the filter device of FIG. 2, since the maximum value Max[n−1:0] and minimum value Min[n−1:0] used in the limiter circuit 20 are fixed, the filter device cannot eliminate the overshoot 21 or undershoot 22 which have values equal to or larger than the set minimum value Min[n−1:0] or less than the maximum value Max[n−1:0].
Conventionally, for example, Japanese Patent Kokai Nos. 8-79558 and 2002-94358 disclose digital filter devices for removing such overshoot 21 and undershoot 22.
Japanese Patent Kokai No. 8-79558 describes a digital filter device which comprises a first low pass filter (hereinafter referred to as the “LPF”) including an FIR digital filter which has a relatively abrupt cut-off characteristics for filtering input digital image data; a second LPF including an FIR digital filter which has a relatively slow cut-off characteristics for filtering the input digital image data; a mixer for mixing the digital image signals filtered by the first and second LFPs, respectively; a step detector for detecting a step-wise change in the value of the input digital image signal; and a controller for controlling a mixing ratio of the digital image signals from the first and second LPFs to be mixed by the mixer on the basis of the step detection output of the step detector. This digital filter device provides a wide flat band and can suppress overshoot.
Japanese Patent Kokai No. 2002-94358 discloses a filter device which comprises a first digital filter for filtering an input signal with an increased number of taps for filter coefficients; a second digital filter for filtering the input signal using a minimally required number of taps to alleviate overshoot and ringing; a high pass filter (hereinafter referred to as the “HPF”) for detecting a portion of the input signal in which a change is found; a boundary signal generator for generating a boundary signal which changes at a constant slope within a range of a boundary between an effective portion of the input signal and a blanking period based on a synchronization signal; a synthesis signal generator for receiving the signals from the HPF and boundary signal generator to output a determination signal; and a synthesizer for receiving the signals from the first and second digital filters to predominantly output the signal from the second digital filter in a portion of the input signal in which no change is found and in a boundary portion between the effective portion of the input signal and the blanking period, and to predominantly output the signal from the digital filter in the remaining portion based on the determination signal. This filter device can suppress the overshoot which can occur during filtering.
However, there are the following problems (a) to (c) to be solved associated with the conventional filter devices:
(a) The filter device of Japanese Patent Kokai No. 8-79558 includes the first and second LPFs for providing a single filtering effect and the mixer for controlling the mixing ratio, resulting in an increased chip area, and cannot completely eliminate the overshoot because the filter device basically involves a switch between the first and second LPFs.
(b) The filter device of Japanese Patent Kokai No. 2002-94358 includes the HPF, and replaces a boundary plane with another signal by the boundary signal generator, synthesis signal generator, and synthesizer to control the mixing ratio, resulting in an increased chip area. Moreover, while a filter is employed for removing a sub-carrier frequency component from a luminance signal, this filter is not necessary and rather adversely affects.
(c) Assuming that Japanese Patent Kokai No. 8-79558 and Japanese Patent Kokai No. 2002-94358 are applied for removing the overshoot 21 and undershoot 22 generated in the filter device of FIG. 2, measures must be taken, such as increasing the number of the filters 10, resulting in not only an increased chip area but also difficulties in removing the overshoot 21 and undershoot 22 without making the circuit configuration complicated.